1. Field of the Invention
The present invention relates to a semiconductor integrated circuit protected from element breakdown and, more particularly, to a semiconductor memory protected from element breakdown.
2. Discussion of the Related Art
MOS transistor cells have been increasingly micropatterned as technology has progressed, and as result semiconductor memories having a larger memory capacity have been developed. The channel length of transistors has become shorter and gate insulating films have become thinner. Therefore, when memory capacity is the same as that of the conventional memory, the chip size of the semiconductor memory is decreased by the microlithography technique, thus providing a lower-cost semiconductor memory.
The arrangement of a conventional nonvolatile semiconductor memory having a MOS transistor with a floating gate as a memory cell is shown in FIG. 1. In this semiconductor memory, whether logic "0" data or logic "1" data is stored is determined depending on whether electrons are injected into a floating gate of a memory cell MC. Data is programmed in this memory cell, when a signal P is a logic "0". A logic level which is the same as input data Din appears at a node A. At this time, a high voltage is applied to a gate X of a memory cell MC, and to a gate Y of a column select transistor 1. When the input data Din is a logic "0", a voltage SW, which is higher in a program mode, is applied to the gate of a write load transistor 2. As a result, the transistor 2 is turned on, and a program voltage Vp is applied to the drain of the memory cell MC. Therefore, electrons are injected into the floating gate of the memory cell MC, and data "0" is written.
On the other hand, when the input data Din is set at a logic "1", the voltage of the gate of the write load transistor 2 is set to be 0 V. As a result, the transistor 2 is turned off. Therefore, the voltage Vp is not applied to the drain of the memory cell MC, and the floating gate is kept in a neutral state.
A write apparatus called a ROM writer is used to write data in the nonvolatile semiconductor memory, i.e., an EPROM shown in FIG. 1.
FIG. 2 shows an arrangement of a conventional booster for generating a voltage SW when data is written (programmed) into the memory cell. As shown in FIG. 3C, the output voltage SW of the booster is equal to a voltage Vc (e.g., 5 V) in a read mode, and is higher than a voltage Vp in a program mode (period T2 in FIG. 3A-3G). The voltage SW is also supplied to circuits such as a decoder which requires a high voltage in the program mode.
When a signal IN1 shown B in FIG. 4B is a logic "1", a transistor T11, shown in FIG. 2, to the gate of which the signal IN1 is input is turned on. A voltage of a node N2, shown in FIG. 2, is 0 V because a discharging operation is performed by a transistor T10 and the turned-on transistor T11. A voltage Vp is supplied to the drain of the transistor T1.
As shown in FIG. 4A, in a program mode, the voltage Vp goes to a high-voltage level (e.g., 12.5 V). As shown in FIG. 4B, in the program mode, data is written in practice during a period T2 when a program mode control signal PGM is a logic "0". Even if the program power source voltage Vp is applied, data is not written during periods T1 and T3 when the signal PGM is a logic "1". The periods T1 and T3 are used to prevent a write error or to perform initialization. For example, the lengths of periods T1 and T3 are determined to give a sufficient time margin for the externally supplied write data Din to reach a data write circuit in the EPROM. During the periods T1 and T3, the voltage Vp is the high voltage. However, since the signal IN1 is a logic "1", the voltage SW is not boosted.
As shown in FIGS. 4C and 4D, in a program mode, the signal IN1 and a signal IN3 are switched to a logic "0" (0 V), and a signal IN2 is switched to a logic "1". When the signal IN2 goes to a logic "1", the transistor T3 is turned on. As shown in FIG. 3C, a voltage obtained by subtracting a threshold voltage (VTH3) of the transistor T3 from a voltage VIN2 of the signal IN2, i.e., a voltage of (VIN2-VTH3) appears at a node N3. The voltage at the node N3 is applied to the gate of a transistor T4, the gate and the drain of which are connected to the node N3, and the transistor T4 is turned on. As a result, as shown in FIG. 3A, a voltage obtained by subtracting a threshold voltage VTH4 of the transistor T4 from the voltage (VIN2-VTH3), i.e., a voltage (VIN2-VTH3-VTH4) appears at the node N1. The voltage (VIN2-VTH3-VTH4) is applied to the gate of a transistor T5, the gate and the drain of which are connected to the node N1, and the transistor T5 is turned on. As a result, as shown in FIG. 3B, a voltage obtained by subtracting a threshold voltage VTH5 of the transistor T5 from the voltage (VIN2-VTH3-VTH4), i.e., a voltage (VIN2-VTH3-VTH4-VTH5) appears at the node N2, and is applied to the gates of the transistors T1 and T2.
If the voltage VIN2 is set to be 5 V, the threshold voltage VTH3 is set to be 1.0 V, and the threshold voltages VTH4 and VTH5 are set to be 0 V (that is, transistors T4 and T5 are "natural" or intrinsic transistors as indicated by the "circle" on their respective gates) to increase a boosting efficiency, a voltage of 4 V appears at the node N2. For this reason, when a boosting operation is started, a potential difference between the gate and the drain of each of the transistors T1 and T2 is set to be (Vp-4) V, and the potential of the node N2 is increased along with the boosting operation. For this reason, the potential difference between the drain and the gate of each of the transistors T1 and T2 is further decreased. Finally, the potential of the gate becomes higher than the potential of the drain.
When data is programmed in the memory cell MC, the higher the voltage applied to the drain of the memory cell MC is, the shorter the program time becomes. For this reason, the voltage SW is set to be higher than the program voltage Vp by, e.g., a threshold voltage of the transistor T2 in order to compensate for a voltage drop of the threshold voltage in the write load transistor 2 shown in FIG. 1. In the conventional nonvolatile semiconductor memory shown in FIG. 1, when data is written in another memory cell MC, a high voltage is applied to the control gate (if in the same row) or the drain (if in the same column) of memory cell MC in which data has already been written, and electrons are injected into the floating gate. Therefore, the electrons previously injected and accumulated in the floating gate are often discharged due to the high voltage applied to the control gate or the drain. In such a case, an erase error of data which has been written undesirably occurs. The thinner the gate insulating film of the memory cell MC, the more often the erase error occurs. In order to prevent such a phenomenon, during a data write operation, the voltage applied to the control gate or the drain of the memory cell must be decreased in correspondence with the reduction of the thickness of the gate insulating film so as to be equal to the conventional intensity of the electric field.
As described above, however, the high voltage Vp for a write operation supplied from the writer is fixed. Therefore, when an EPROM, in which a micropatterned transistor is employed to reduce costs and decrease chip size, is developed and the program voltage Vp is set at a low value in order to prevent an erase error of the data, a new writer having a lower output voltage Vp as the program voltage must be developed. However, it is not practical to develop a new writer each time a new EPROM is developed.
In order to solve the above problem, there is proposed a highly reliable semiconductor integrated circuit in Japanese Patent Publication (Kokai) No. 58-115411. In this semiconductor integrated circuit, even if elements are micropatterned under the condition that an externally supplied power source voltage is fixed, an erase error of data does not occur. In this proposal, there is provided a semiconductor integrated circuit wherein a gate voltage of a voltage conversion MOSFET is controlled in correspondence with a reference voltage, so that a constant internal power source voltage lower than the external power source voltage can be obtained from one terminal of the voltage conversion MOSFET.
FIG. 5 is a circuit diagram showing an arrangement of a nonvolatile memory disclosed in this proposal. Referring to FIG. 5, an EPROM circuit 41 has all the functions of a memory, and includes the memory cell MOSFETs (shown in FIG. 1) including the column select MOSFET 1, the data write MOSFET 2, and row and column decoders. The EPROM circuit 41 includes an external power source terminal 42 to which the power source voltage Vc (e.g., 5 V) is supplied, an external power source terminal 43 to which a voltage Vp is supplied in a data write mode, and an internal power source terminal 44 to which a constant voltage Vpp lower than the voltage Vp is supplied, the voltage Vpp being supplied to a memory cell MOSFET in the EPROM circuit 41 in the data write mode.
A MOSFET 51 is inserted between the external and internal power source terminals 43 and 44 to convert the voltage Vp supplied to the terminal 43 into the voltage Vpp lower than the voltage Vp. In addition, a reference voltage generator 54, including series-connected resistors 52 and 53, is inserted between the external terminal 43 and a ground potential Vss. In the reference voltage generator 54, a reference voltage VREF obtained by dividing the voltage Vp in accordance with the ratio of resistances of the resistors 52 and 53 is output from a connection node 55 between the resistors 52 and 53. In addition, a controller 58 in which a depletion type MOSFET 56 and an enhancement type MOSFET 57 is series-connected is inserted between the external power source terminal 43 and the node 55. The source of the FET 56 and the drain of the FET 57 are connected. In the controller 58, the gate of the MOSFET 56 and the gate of the voltage conversion MOSFET 51 are connected to a connection node 59 between the MOSFETs 56 and 57, and the gate of the MOSFET 57 is connected to the internal power source terminal 44, i.e., the source of the voltage conversion MOSFET 51. More specifically, the controller 58 serves as an inverting amplifier having the depletion type MOSFET 56 serving as a load transistor, and the enhancement type MOSFET 57 serving as a drive transistor. As a result, a voltage corresponding to a difference between the voltage Vpp at the internal power source terminal 44 and the reference voltage VREF appears at the node 59.
With such an arrangement, when the voltage Vpp at the internal power source terminal 44 is changed from a stable voltage to a lower voltage than the stable voltage, the conduction state of the MOSFET 57 in the controller 58 gets an OFF state, and the resistance between the source and the drain of the MOSFET 57 is increased. When the resistance is increased, the voltage of the node 59 is increased accordingly. Therefore, the conduction state of the MOSFET 51 gets near a stronger ON state, and the voltage Vpp at the terminal 44 returns to the original value. On the other hand, when the voltage Vpp at the internal power source terminal 44 is changed from a stable voltage to a higher voltage than the stable voltage, the MOSFET 51 gets near a stronger ON state, and the resistance between the source and the drain of the MOSFET 57 is decreased. Therefore, the voltage of the node 59 is decreased, the MOSFET 51 gets almost to an OFF state, and, hence, the voltage Vpp returns to the original value. In other words, the gate of the MOSFET 51 is controlled by the controller 58, so that the voltage Vpp of the internal power source terminal 44 is always kept at a constant value.
The voltage Vpp at the internal power source terminal 44 and an output voltage Vo from the controller 58 are defined as follows: EQU Vpp=VREF+VTH2 (1) EQU Vpp=Vo-VTH1 (2)
where VTH1 is the threshold voltage of the MOSFET 51, VTH2 is a threshold voltage of the MOSFET 57, and Vo is a voltage at the node 59 of the controller 58, i.e., an output voltage of the controller 58.
As is apparent from equation (1), the voltage Vpp is controlled to be equal to a sum of the voltages VREF and VTH2. Note that the resistance ratio of the resistors 52 and 53 in the reference voltage controller 54 is controlled, so that the reference voltage VREF can be arbitrarily set to be a voltage lower than the voltage Vp supplied to the terminal 43. For this reason, the voltage Vpp at the internal power source terminal 44 can always be a substantially constant voltage lower than the voltage Vp. For example, the voltage Vpp obtained at the internal power source terminal 44 is supplied to the control gate of the memory cell MOSFET (FIG. 1) in the EPROM circuit 41. For this reason, even if the memory cell MOSFET is micropatterned compared to the conventional one, and the thickness of the gate insulating film thereof is thinner, the voltage Vpp, lower than the voltage Vp supplied to the external power source terminal 43, is applied to the memory cell's control gate. Therefore, even if the write output voltage Vp of the writer for supplying the voltage Vp to the terminal 43 is fixed, no erase error of data as in the conventional case occurs. Therefore, the value of the write output voltage Vp in the writer need not be changed for each memory, and the conventional writer can be commonly used.
More specifically, even if the memory cell MOSFET is micropatterned under the condition that the externally supplied data write power source voltage Vp is fixed, an erase error of data does not occur, and a reliable operation is achieved.
FIG. 6 shows an arrangement of a nonvolatile memory according to a modification of the circuit shown in FIG. 5. The arrangement in FIG. 6 is different from that in FIG. 5 as follows. In FIG. 6, a MOSFET 60 is inserted between a MOSFET 51 and a terminal 43, and a MOSFET 61 is inserted between a resistor 53 and a ground potential Vss. A signal H, higher than the voltage Vp, is supplied to the gate of the MOSFET 60 in a program mode. A signal SV which is set at a logic "1" in the program mode to cause the transistor 61 to turn on is supplied to the gate of the MOSFET 61.
In this circuit, both the MOSFETs 60 and 61 are 10 turned OFF in any mode except for the program mode. Therefore, a current is not supplied to the MOSFET 51, a reference voltage generator 54, and a controller 58, and current consumption can be decreased.
In the program mode, a high voltage Vp is applied to the terminal 43. When an externally input control signal is set at a predetermined logic level while the high voltage Vp is applied to the terminal 43, a data write operation is performed. For this reason, a circuit for detecting that the voltage Vp becomes a high voltage is arranged in the integrated circuit. The integrated circuit also has a verification function to check whether correct data is written. The verifying operation is performed while the high voltage Vp is kept applied to simplify an ON/OFF operation of the externally supplied power source voltage.
FIGS. 7A to 7F are timing charts, in a program mode, of the conventional 256 k-bit EPROM and in a program verify mode. When an externally applied chip enable signal CE is set at "0" level as shown in FIG. 7B, and an output enable signal OE is set at "1" level as shown in FIG. 7C, a program operation is performed, i.e., data is written. When the signal CE is "1" and the signal OE is "0", a verify mode is obtained. At this time, in the integrated circuit, the signals SV and H shown in FIG. 6 are as follows. When the high voltage vp is applied to the terminal 43, this application is sensed, and the signal SV goes to "1" level, and the MOSFET 61 in FIG. 6 is turned on. On the other hand, when the signal CE is logic "0" and the signal OE is logic "1" in a program mode, the signal H is set at a high voltage. As a result, as described above, a voltage Vpp lower than the external power source voltage Vp by a predetermined voltage is supplied to the EPROM circuit only in the program mode. For this reason, a mode wherein the high voltage Vp is applied to the terminal 43 while the signal H is kept at 0 V and the MOSFET 60 is kept OFF is present.
Referring to FIGS. 8A and 8B, the EPROM will be described in detail. Each of write control signal generators 71-1 to 71-n outputs a write control signal having different output states in accordance with logical states of write data. Each of write load circuits 72-1 to 72-n determines in response to the write control signal whether or not a write voltage to write the data in a nonvolatile memory cell is to be output. Column selectors 74-11 to 74-x1, . . ., 74-1n to 74-xn constituting the first to the xth stages select corresponding data lines DL-11 to DL-n1 of a nonvolatile memory cell array 73. Select signal generators 75-11 to 75-1m, . . ., 75-x1 to 75-xl constituting the first to the xth stages control the corresponding column selectors. For example, when a memory cell 77-xl is selected, transistors 76-11 and 76-xl are selected.
As described above, the thickness of a gate insulating film is further decreased along with micropatterning of a semiconductor integrated circuit, and the depths of diffusion layers in diffusion regions of the drain and the source are also decreased. As a result, the breakdown voltage at the drain region of the transistor is decreased. For this reason, when a nonvolatile semiconductor memory is manufactured using a further micropatterned transistor, the transistor must be used in a voltage region wherein the drain breakdown does not occur.
In general, an electric field for causing the breakdown at the drain of a MOSFET is weaker than that for causing breakdown at a p-n junction. The lower the gate voltage is, the lower the drain breakdown voltage becomes. For example, when the potential of a gate B is 0 V, the drain breakdown voltage of the write load transistor 2 shown in FIG. 1 is a minimum value. If the breakdown occurs in the transistor to which the voltage Vp is supplied from the external power source, a sufficient current is supplied from the external power source, so that the breakdown does not stop, thus destroying the transistor. For example, the breakdown does not occur at a voltage which is normally used. However, if noise is added to the voltage Vp and the voltage Vp exceeds the breakdown voltage, the breakdown occurs. At this time, if decisive breakdown occurs, negative-resistance characteristics are exhibited, and the breakdown does not stop. As a result, the transistor may often be broken.
In the circuit shown in FIG. 2, the potential of the node N2 is 0 V during the periods T1 and T3 and is not OV for the period T2 when data is written in practice. Therefore, a potential difference between the drain and the gate of each of the transistors T1 and T2 is equal to the voltage Vp, and the strongest electric field is obtained. For this reason, when the thickness of the gate insulating film is decreased because of micropatterning of elements, the possibility that the gate insulating film will be damaged is increased during the periods T1 and T3 when the electric field is the strongest. If a countermeasure against this problem is not taken, micropatterning of elements cannot be achieved. In the future, the thickness of the gate insulating film will be decreased as micropatterning is advanced, and elements will further tend to be damaged in the above circuit arrangement.
In FIG. 6, the number of transistors having a gate insulating film to which a strong electric field is applied is small compared to the conventional case, and the probability of the gate insulating film being damaged is decreased. However, the electric field between the drain and the gate in the MOSFET 60 is strong, and the gate insulating film between the drain and the gate may be damaged. The MOSFET 61 also has the same probability for being damaged. More specifically, in the transistor 61, a voltage set at 0 V of the signal SV is applied to the gate, and a high voltage is applied to the drain, after a high voltage is applied as the voltage Vp until the high voltage is sensed and the signal SV is set at "1" level. Meanwhile, the electric field between the drain and the gate of the MOSFET 61 has a high intensity, and the possibility for damaging the gate insulating film is increased.
In the circuit shown in FIGS. 8A and 8B, when the transistor 76-11, in the first column selector, 74-11 is selected, an output from the write load circuit 72-1 is equal to the voltage Vp. However, since outputs from the select signal generators 75-12 to 75-1m are set to be 0 V, the intensity of the electric field between the gate and the drain of each of the transistors 76-12 to 76-1m is increased, and the possibility of damaging the gate insulating film is increased. In addition, when the transistor 76-11 is selected and a high voltage is applied to its gate, a high voltage is not often output from the write load circuit depending on write data. At this time, the intensity of the electric field between the gate and the channel of the transistor 76-11 is maximum, and damage to the gate insulating film may occur.
As described above, when the thickness of the gate insulating film of the MOSFET is decreased, the electric field applied to the gate insulating film is so strong that not only the MOSFET but also its peripheral transistors may often be damaged. In addition, the problems caused by micropatterning of elements are posed in not only the nonvolatile memory, but also in other memories. Thus, in the conventional circuit, the problems such as an erase error of data or breakdown of elements are posed because of micropatterning of the elements, thus degrading reliability.